View UPD72852AGB-8EU_4264921.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2003 the mark shows major revised points. pd72852a mos integrated circuit data sheet ieee1394a-2000 compliant 400 mbps two-port phy lsi document no. s16725ej2v0ds00 (2nd edition) date published march 2004 ns cp (k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. the pd72852a is a two-port physical layer lsi that complies with the ieee 1394a-2000 specifications. features ? the two-port physical layer lsi complies with ieee1394a-2000 ? fully interoperable with i eee1394 std 1394 link (firewire tm , i.link tm ) ? meets intel tm mobile power guideline 2000 ? full ieee1394a-2000 support includes: suspend/resume, connec tion debounce, arbitrated shor t bus reset, multi-speed concatenation, arbitration acce leration, fly-by concatenation ? suspend debounce timer for esd ? ?bias detected? signal output ? double speed signal filter for bias ringing ? small package: 64-pin plastic lqfp ? super low power : 68 ma (operating mode) : 115 a (suspend mode) ? data rate: 400/200/100 mbps ? supports phy pinging and remote phy access packets ? 3.3 v single power supply (if power not s upplied via node: 3.0 v single power supply) ? 24.576 mhz crystal clock generation, 393.216 mhz pll multiplying frequency ? 64-bit flexible register in corporated in phy register ? electrically isolated link interface ? supports lps/link-on as part of phy/link interface ? external filter capacit ors for pll not required ? extended resume signaling for com patibility with legacy dv devices ? system power management by signaling of node power class information ? cable power monitor (cps) is equipped ordering information part number package pd72852agb-8eu 64-pin plastic lqfp (10 10)
data sheet s16725ej2v0ds 2 pd72852a block diagram link interface i/o voltage and current generator cable power status crystal oscillator pll system and transmit clock generator receive data decoder and retimer transmit data encoder arbitration and control state machine logic lreq lps direct sclk lkon ctl0 ctl1 d0 d1 d2 d3 d4 d5 d6 d7 cmc pc0 pc1 pc2 sus/res tpa0p tpa0n tpb0p tpb0n cable port0 cable port1 tpbias0 tpbias1 ri1 xi xo resetb cps tpa1p tpa1n tpb1p tpb1n bdb
data sheet s16725ej2v0ds 3 pd72852a pin configuration (top view) ? pd72852agb-8eu 64-pin plastic lqfp (10 10) dgnd sclk ic(dl) dv dd ctl0 ctl1 dgnd d0 d1 dv dd d2 d3 dgnd d4 d5 dgnd tpbias1 av dd tpa1p tpa1n tpb1p tpb1n agnd tpbias0 av dd tpa0p tpa0n tpb0p tpb0n agnd ri1 agnd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d6 d7 sus/res dv dd dgnd xo xi agnd av dd pc0 pc1 pc2 ic(al) cmc av dd cps dgnd lreq fnsel spd/bdb dv dd lps lkon dgnd dv dd resetb av dd agnd agnd ic(al) direct agnd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
data sheet s16725ej2v0ds 4 pd72852a pin name agnd : analog gnd av dd : analog power cmc : configuration manager capable cps : cable power status ctl0 : link interface control (bit 0) ctl1 : link interface control (bit 1) d0-d7 : data input/output dgnd : digital gnd direct : phy/link isolat ion barrier control input dv dd : digital v dd fnsel : function select ic(al) : internally connected (low clamped) ic(dl) : internally connected (low clamped) lkon : link-on signal output lps : link power status input lreq : link request input pc0-pc2 : power class set input resetb : power-on reset input ri1 : reference power set, connect resistor 1 sclk : link control output clock spd/bdb : speed select input / bias detected output sus/res : suspend/resume function select tpa0n : port 0 twisted pair cable a negative phase i/o tpa0p : port 0 twisted pair cable a positive phase i/o tpa1n : port 1 twisted pair cable a negative phase i/o tpa1p : port 1 twisted pair cable a positive phase i/o tpb0n : port 0 twisted pair cable b negative phase i/o tpb0p : port 0 twisted pair cable b positive phase i/o tpb1n : port 1 twisted pair cable b negative phase i/o tpb1p : port 1 twisted pair cable b positive phase i/o tpbias0 : port 0 twisted pair output tpbias1 : port 1 twisted pair output xi : crystal oscillator connection xi xo : crystal oscillator connection xo
data sheet s16725ej2v0ds 5 pd72852a contents 1. pin functio ns............................................................................................................. ........................ 7 1.1 cable in terface pins ...................................................................................................... .................. 7 1.2 link in terface pins ....................................................................................................... ................... 7 1.3 cont rol pins .............................................................................................................. ....................... 8 1.4 ic ........................................................................................................................ ............................... 8 1.5 power supply pins ......................................................................................................... ................. 8 1.6 othe r pins ................................................................................................................ ........................ 9 2. phy re gisters .............................................................................................................. .................... 10 2.1 complete structur e for phy re gisters ...................................................................................... . 10 2.2 port status page (p age 000) ............................................................................................... ......... 13 2.3 vendor id page (p age 001)................................................................................................. .......... 14 2.4 vendor dependent page (page 111 : port _select 0000)............................................................ 14 2.5 vendor dependent page (page 111 : port _select 0001)............................................................ 15 3. internal funct ion.......................................................................................................... ................ 16 3.1 link interf ace ............................................................................................................ ..................... 16 3.1.1 connec tion me thod ....................................................................................................... ........................ 16 3.1.2 lps (link power status) ................................................................................................. ...................... 16 3.1.3 lreq, ctl0, ctl1 and d0-d 7 pi ns......................................................................................... ............ 16 3.1.4 sclk.................................................................................................................... ................................. 16 3.1.5 lkon .................................................................................................................... ................................ 17 3.1.6 dire ct.................................................................................................................. ............................... 17 3.1.7 isolat ion ba rrier ....................................................................................................... .............................. 17 3.2 cable interf ace........................................................................................................... .................... 19 3.2.1 c onnecti ons ............................................................................................................. ............................. 19 3.2.2 cable in terface circu it................................................................................................. .......................... 20 3.2.3 unus ed port s ............................................................................................................ ............................ 20 3.2.4 cps..................................................................................................................... .................................. 20 3.3 suspe nd/resume ............................................................................................................ .............. 20 3.3.1 suspend/resume on mode (sus/r es = ?h?).................................................................................. .... 20 3.3.2 suspend/resume off mode (sus/r es = ?l?) ................................................................................. ..... 20 3.4 pll and crystal oscillation circuit ....................................................................................... ...... 21 3.4.1 crystal o scillation circu it ............................................................................................. ......................... 21 3.4.2 pll..................................................................................................................... ................................... 21 3.5 cmc ....................................................................................................................... ......................... 21 3.6 pc 0-pc2 ................................................................................................................... ...................... 21 3.7 resetb .................................................................................................................... ...................... 21 3.8 ri1 ....................................................................................................................... ............................ 21 4. phy/li nk inte rface ......................................................................................................... ................ 22 4.1 initialization of link power st atus (lps) and phy/ link inte rface ............................................ 22 4.2 link-on indicat ion ........................................................................................................ ................. 23 4.3 phy/link interface operati on (ctl0, ctl1, lr eq, d0-d 7) ...................................................... 24 4.3.1 ct l0, ct l1 .............................................................................................................. ............................ 24 4.3.2 lreq .................................................................................................................... ................................ 24
data sheet s16725ej2v0ds 6 pd72852a 4.3.3 sclk timing ............................................................................................................. ............................ 28 4.4 accelerat ion cont rol ...................................................................................................... ............... 29 4.5 transm it st atus ........................................................................................................... .................. 30 4.6 tr ansmit .................................................................................................................. ....................... 31 4.7 ca ncel.................................................................................................................... ......................... 32 4.8 r eceive ................................................................................................................... ........................ 33 5. cable ph y packet ........................................................................................................... ................ 34 5.1 self _id p acket............................................................................................................ .................... 34 5.2 link -on p acket............................................................................................................ ................... 35 5.3 phy confi guration packet.................................................................................................. .......... 35 5.4 extende d phy packet ....................................................................................................... ............ 35 5.4.1 pi ng packe t ............................................................................................................. .............................. 36 5.4.2 remote access pa cket .................................................................................................... ..................... 36 5.4.3 remote reply packe t..................................................................................................... ....................... 37 5.4.4 remote command pa cket ................................................................................................... ................. 37 5.4.5 remote c onfirmation packet .............................................................................................. .................. 38 5.4.6 resu me pa cket........................................................................................................... .......................... 38 6. electrical specifi cations .................................................................................................. ....... 39 7. applicatio n circuit example ................................................................................................ ..... 44 8. packag e drawin g............................................................................................................ ............... 45 9. recommended sold ering condi tions .................................................................................. 46
data sheet s16725ej2v0ds 7 pd72852a 1. pin functions 1.1 cable interface pins name pin no. i/o function tpa0p 39 i/o port 0 twisted pair cable a positive phase i/o tpa0n 38 i/o port 0 twisted pair cable a negative phase i/o tpb0p 37 i/o port 0 twisted pair cable b positive phase i/o tpb0n 36 i/o port 0 twisted pair cable b negative phase i/o tpa1p 46 i/o port 1 twisted pair cable a positive phase i/o tpa1n 45 i/o port 1 twisted pair cable a negative phase i/o tpb1p 44 i/o port 1 twisted pair cable b positive phase i/o tpb1n 43 i/o port 1 twisted pair cable b negative phase i/o sus/res 19 i suspend/resume function select 1: suspend/resume on (ieee1394a-2000 compliant) 0: suspend/resume off (p1394a draft 1.3 compliant) cps 32 i cable power status connect to the cable through a 390 k ? resistor and to gnd through a 100 k ? resistor. 0: cable power fail 1: cable power on 1.2 link interface pins name pin no. i/o function d0 8 i/o data input/output (bit 0) d1 9 i/o data input/output (bit 1) d2 11 i/o data input/output (bit 2) d3 12 i/o data input/output (bit 3) d4 14 i/o data input/output (bit 4) d5 15 i/o data input/output (bit 5) d6 17 i/o data input/output (bit 6) d7 18 i/o data input/output (bit 7) ctl0 5 i/o link interface control (bit 0) ctl1 6 i/o link interface control (bit 1) lreq 63 i link request input sclk 2 o link control output clock lps 1: 49.152 mhz output lps 0: clamp to 0 (the clock signal will be output within 25 sec after change to ?0?) lps 59 i link power status input 0: link power off 1: link power on (phy/link direct connection) lkon 58 o link-on signal output link-on signal is 6.144 mhz clock output. please refer to 4.2 link-on indication . direct 50 i phy/link isolation barrier control input 0: isolation barrier 1: phy/link direct connection
data sheet s16725ej2v0ds 8 pd72852a 1.3 control pins name pin no. i/o function pc0 26 i pc1 27 i pc2 28 i power class set input this pin status will be loaded to pwr_class bit which allocated to phy register 4h. ieee1394a-2000 chapter [4.3.4.1] cmc 30 i configuration manager capable setting this pin status will be loaded to contender bi t which allocated to phy register 4h. 0: non contender 1: contender resetb 55 i power-on reset input connect to gnd through a 0.1 f capacitor. 0: reset 1: normal fnsel 62 i function select 0: #61 acts as spd 1: #61 acts as bdb spd 61 i speed select ( when fnsel set to 0 ; pd72852a compliant) 0: max. s200 1: max. s400 bdb 61 o bias detected (logical inverse) 0: bias is detected after suspend debounce timer. 1: bias is not detected. 1.4 ic name pin no. i/o function ic(al) 29, 51 - internally connected (low clamped) connect to gnd. ic(dl) 3 - internally connected (low clamped) connect to gnd. 1.5 power supply pins name pin no. i/o function av dd 25, 31, 40, 47, 54 - analog power agnd 24, 33, 35, 42, 49, 52, 53 - analog gnd dv dd 4, 10, 20, 56, 60 - digital v dd dgnd 1, 7, 13, 16, 21, 57, 64 - digital gnd
data sheet s16725ej2v0ds 9 pd72852a 1.6 other pins name pin no. i/o function tpbias0 41 o port 0 twisted pair output tpbias1 48 o port 1 twisted pair output ri1 34 - resistor connection pin1 for reference current generator connect to gnd through a 9.1 k ? resistor. xi 23 - crystal oscillator connection xi xo 22 - crystal oscillator connection xo
data sheet s16725ej2v0ds 10 pd72852a 2. phy registers 2.1 complete structure for phy registers figure 2-1. complete structure of phy registers 0 1 2 3 4 5 6 7 0000 physical_id r ps 0001 rhb ibr gap_count 0010 extended (7) reserved total_ports 0011 max_speed reserved delay 0100 link_active contender jitter pwr_class 0101 watchdog isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 reserved 0111 page_select reserved port_select 1000 register0 (page_select) 1001 register1 (page_select) 1010 register2 (page_select) 1011 register3 (page_select) 1100 register4 (page_select) 1101 register5 (page_select) 1110 register6 (page_select) 1111 register7 (page_select) table 2-1. bit field description (1/3) field size r/w reset value description physical_id 6 r 000000 physical_id value selected from self_id period. r 1 r 0 if this bit is 1, the node is root. 1: root 0: not root ps 1 r cable power status. 1: cable power on 0: cable power off rhb 1 r/w 0 root hold -off bit. if 1, becomes root at the bus reset. ibr 1 r/w 0 initiate bus reset. setting to 1 begins a long bus reset. long bus reset signal duration: 166 sec. returns to 0 at the beginning of bus reset. gap_count 6 r/w 111111 gap count value. it is updated by the changes of transmitting and receiving the phy configuration packet tx/rx. the value is maintained after first bus reset. after the second bus reset it returns to reset value. extended 3 r 111 shows the extended register map.
data sheet s16725ej2v0ds 11 pd72852a table 2-1. bit field description (2/3) field size r/w reset value description total_ports 4 r 0010 supported port number. 0010: 2 ports max_speed 3 r see description indicate the maximum speed that this node supports. set variable by spd pin (61 pin). when spd = ?0? then 001: 98.304 and 196.608 mbps. when spd = ?1? then 010: 98.304, 196.608 and 393.216 mbps. delay 4 r 0000 indicate worst case repeating delay time. 144 + (delay 20) = 144 nsec link_active 1 r/w 1 link active. 1: enable 0: disable the logical and status of this bit and lps pin. state will be referred to ?l bit? of self-id packet#0. contender 1 r/w see description contender. ?1? indicate this node support bus manager function. this bit will be referred to ?c bit? of self-id packet#0. the reset data is depending on cmc pin setting. cmc pin condition 1: pull up (contender) 0: pull down (non contender) jitter 3 r 010 the difference of repeating time (max.-min.). (2+1) 20 = 60 nsec pwr_class 3 r/w see description power class. please refer to ieee1394a-2000 [4.3.4.1]. this bit will be referred to pwr field of self-id packet#0. the reset data will be determined by pc0-pc2 pin status. watchdog 1 r/w 0 watchdog enable. this bit serves two purposes. when set to 1, if any one port does resume, the port_event bit becomes 1. this function has no effect when sus/res (19 pin) = ?0?. to determine whether or not an interrupt condition shall be indicated to the link. on condition of lps = 0 and watchdog = 0, lkon as interrupt of loop, pwr_fail, timeout is not output. this function has effect both when sus/res (19 pin) = ?1? or ?0?. isbr 1 r/w 0 initiate short (arbitrated) bus reset. setting to 1 acquires the bus and begins short bus reset. short bus reset signal output : 1.3 sec returns to 0 at the beginning of the bus reset. loop 1 r/w 0 loop detection output. 1: detection writing 1 to this bit clears it to 0. writing 0 has no effect. pwr_fail 1 r/w 1 power cable disconnect detect. it becomes 1 when there is a change from 1 to 0 in the cps bit. writing 1 to this bit clears it to 0. writing 0 has no effect.
data sheet s16725ej2v0ds 12 pd72852a table 2-1. bit field description (3/3) field size r/w reset value description timeout 1 r/w 0 arbitration state machine time-out. writing 1 to this bit clears it to 0. writing 0 has no effect. port_event 1 r/w 0 set to 1 when the int_enable bit in the register map of each port is 1 and there is a change in the ports connected, bias, disabled and fault bits. set to 1 when the watchdog bit is 1 and any one port does resume. writing 1 to this bit clears it to 0. writing 0 has no effect. this bit is not settable when sus/res (19 pin) = ?0?. enab_accel 1 r/w 0 enables arbitration acceleration. ack-acceleration and fly-by arbitration are enabled. 1: enabled 0: disabled if this bit changes while the bus request is pending, the operation is not guaranteed. enab_multi 1 r/w 0 enable multi-speed packet concatenation. setting this bit to 1 follows multi-speed transmission. when this bit is set to 0,the packet w ill be transmitted with the same speed as the first packet. page_select 3 r/w 000 select page address between 1000 to 1111. 000: port status page 001: vendor id page 111: vendor dependent page others: unused port_select 4 r/w 0000 port selection. selecting 000 (port status page) with the page_select selects the port. selecting 111 (vendor dependent page) with the page_select have to select the port 1. 0000: port 0 0001: port 1 others: unused reserved - r 000? reserved. read as 0.
data sheet s16725ej2v0ds 13 pd72852a 2.2 port status page (page 000) figure 2-2. port status page 0 1 2 3 4 5 6 7 1000 astat bstat child connected bias disabled 1001 negotiated_speed int_enable fault reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 2-2. bit field description field size r/w reset value description astat 2 r xx a port status value. 00: invalid, 10: ?0? 01: ?1?, 11: ?z? bstat 2 r xx b port status value. 00: invalid, 10: ?0? 01: ?1?, 11: ?z? child 1 r child node status value. 1: connected to child node 0: connected to parent node connected 1 r 0 connection status value. 1: connected 0: disconnected bias 1 r bias voltage status value. 1: bias voltage 0: no bias voltage disabled 1 r/w see description the reset value is set to 0: enabled. negotiated_ speed 3 r shows the maximum data transfer rate of the node connected to this port. 000: 100 mbps 001: 200 mbps 010: 400 mbps int_enable 1 r/w 0 when set to 1, the port_event is set to 1 if any of this port's connected, bias, disabled or fault bits change state. this bit has no effect when sus/res (19 pin) = ?0?. fault 1 r/w 0 set to 1 if an error occurs during suspend/resume. writing 1 to this bit clears it to 0. writing 0 has no effect. this bit has no effect when sus/res (19 pin) = ?0? reserved - r 000? reserved. read as 0.
data sheet s16725ej2v0ds 14 pd72852a 2.3 vendor id page (page 001) figure 2-3. vendor id page 0 1 2 3 4 5 6 7 1000 compliance_level 1001 reserved 1010 1011 1100 vendor_id 1101 1110 1111 product_id table 2-3. bit field description field size r/w reset value description compliance_level 8 r 00000001 according to ieee1394a-2000. vendor_id 24 r 00004ch company id code value, nec ieee oui. product_id 24 r product code. reserved - r 000? reserved. read as 0. 2.4 vendor dependent page (page 111 : port_select 0000) figure 2-4. vendor dependent page 0 1 2 3 4 5 6 7 1000 reserved 1001 reserved long debounce reserved 1010 1011 reserved 1100 w_spd_ dis 1101 1110 1111 rerserved
data sheet s16725ej2v0ds 15 pd72852a table 2-4. bit field description field size r/w reset value description long debounce 2 r/w 00b 00: suspend debounce timer sets to 420 ns 11: suspend debounce timer sets to 1000 ns. w_spd_dis 1 r/w 0 0: not receive double speed signal only first speed signal will be repeated for next port and packet will be decoded by highest speed within received. 1: receive double speed si gnal (ieee1394a-2000 complient). second speed signal will be applied for repeating /decoding. 2.5 vendor dependent page (page 111 : port_select 0001) figure 2-5. vendor dependent page contd. 0 1 2 3 4 5 6 7 1000 1001 1010 1011 1100 1101 1110 1111 reg_array table 2-5. bit field description field size r/w reset value description reg_array 64 r/w 0 this register array is possible r/w.
data sheet s16725ej2v0ds 16 pd72852a 3. internal function 3.1 link interface 3.1.1 connection method figure 3-1. phy/link connection method link phy pd72852a d0-d7 ctl0,ctl1 direct lps lkon sclk lreq note note clamping to v dd provides direct connection to link. clamping to gnd connects through isolation barrier to link. the isolation barrier connection circuit is described in 3.1.7 isolation barrier. 3.1.2 lps (link power status) lps is a function to monitor the on/off stat us of the link power supply. after 1.2 sec or more, lps is low, the phy/link is reset and d and ctl are output low (w hen the isolation barrier is hi-z). after 2.5 sec or more, lps is low, moreover, the phy stops the supply of sclk and sc lk outputs low (when the isolation barrier is hi-z). 3.1.3 lreq, ctl0, ctl1 and d0-d7 pins lreq : indicates that a request is received from link. ctl0, ctl1 : bi-directional pin which controls the functions between the phy/link interface. d0-d7 : bi-directional pin which controls the dat a transfer/receive status signal, and the speed code transfer/receive status signal. 3.1.4 sclk 49.152 mhz clock supplied by phy for the phy/link interface synchronization.
data sheet s16725ej2v0ds 17 pd72852a 3.1.5 lkon when the link power is off, it output s a clock of 6.144 mhz. lkon outputs under the following conditions: lps is low and the internal phy register of the link_active bit is 0. ? link-on packet is received. ? any bit of loop, pwr_fail, timeout or port_event is the phy internal register becomes 1, and moreover either lps or link_active bit is 0. when lps is asserted, lkon returns to low. 3.1.6 direct set direct to low for using the isolation barrier. 3.1.7 isolation barrier the ieee1394 cable holds signals for data/strobe in addition to power and ground. when the ground potential is different between connecting devices, the dc and ac current flows through the ground line in the cable and there is a possibility of malfunction due to gr ound difference between the two phy. the pd72852a uses the isolation barrier to couple the ac between the phy/li nk interface to overcome the ground difference problem. connecting the direct pin to low enables the digital differential circuit of the pd72852a. the differential circuit propagat es only the change in the signal; the interface will be driven only during transitions high low or low high. the interface will assume the high impedance state when there is no signal change. the pd72852a uses schmitt trigger input buffers for d, ctl, lreq and lps pins to prevent noise when the bus assumes a high impedance state. the digital differential circuit and the schmitt trigger i nput buffers are needed on the link layer controller lsi to implement the isolation barrier. figure 3-2. waveforms of the isolation barrier isolation barrier not used 0 1 1 0 0 0 1 0 0 using isolation barrier (digital differential circuit) 0 1 z 0 z z 1 0 z
data sheet s16725ej2v0ds 18 pd72852a figure 3-3. isolation barrier circuits 5 k ? 0.001 f 5 k ? 5.6 k ? 4.7 k ? link pd72852a (a) ctl0, ctl1, d0-dn isolation barrier circuit gnd dv dd linkv dd linkgnd linkgnd 0.001 f 100 ? 300 ? required when linkv dd is 5 v 5 k ? 1.6 k ? link pd72852a (b) link-on isolation barrier circuit linkv dd linkgnd 0.01 f 100 ? link pd72852 a (c) lps isolation barrier circuit 5k ? 1.6 k ? dv dd gnd 0.033 f 100 ? 5k ? 0.001 f 5 k ? 5.6 k ? 4.7 k ? link pd72852 a (d) lreq isolation barrier circuit gnd dv dd linkv dd linkgnd linkgnd 0.001 f 100 ? 300 ? required when linkv dd is 5 v 5 k ? 0.001 f 5 k ? 5 k ? 5 k ? link pd72852 a (e) sclk isolation barrier circuit gnd dv dd linkv dd linkgnd the operating range of t he power supply voltage is between 3.0 v and 3.45 v. please refer to ieee1394a-2000 [5a.8.4] .
data sheet s16725ej2v0ds 19 pd72852a 3.2 cable interface 3.2.1 connections figure 3-4. cable interface + ? + ? + ? + ? + ? + ? 56 ? 56 ? 7 k ? 7 k ? c onnection detection c urrent connection detection comparato r tpap tpbias tpan drive r receive r arbitration comparators common mode comparators + ? + ? + ? + ? 56 ? 56 ? 7 k ? 7 k ? tpbp tpbn drive r receive r arbitration comparators tpbias detection comparato r common mode speed current drive r 1 f 270 pf 5.1 k ? + ? + ? + ? + ? + ? + ? 56 ? 56 ? 7 k ? 7 k ? connection detection current connection detection comparato r tpap tpbias tpan drive r receive r a rbitration comparators common mode comparators 1 f + ? + ? + ? + ? 56 ? 56 ? 7 k ? 7 k ? tpbp tpbn drive r receive r a rbitration comparators tpbias detection comparato r common mode speed current drive r 270 pf 5.1 k ?
data sheet s16725ej2v0ds 20 pd72852a 3.2.2 cable interface circuit each port is configured with two twisted-pairs of tpa and tpb. tpa and tpb are used to monitor the state of the transmit/receive line, control signals, data and cables. during transmission to the ieee1394 bus, the data/strobe signal received from the link layer controller is encoded, converted from parallel to serial and transmitted. while receiving from the ieee1394 bus, the data/strobe signal from tpa, tpb is converted from serial to parallel after synchronization by sclk, then transmitted to the link laye r controller in 2/4/8 bits a ccording to the data rate of 100/200/400 mbps. the bus arbitration for tpa and tpb and t he state of the line are m onitored by the built-in co mparator. the state of the ieee1394 bus is transmitted to the state machine in the lsi. 3.2.3 unused ports tpap, tpan : not connected tpbp, tpbn : gnd tpbias : not connected 3.2.4 cps connect an external resistor of 390 k ? between the cps pin and the power cabl e, and an external resistor of 100 k ? between the cps pin and gnd to monito r the power of the power cable. if the cable power falls under 7.5 v there is an indication to the link layer controller that the power has failed. 3.3 suspend/resume 3.3.1 suspend/resume on mode (sus/res = ?h?) there are two ways of transition from t he active status to the suspended status. one is when the receipt of a remote command packet that sets the initiate suspend command. after that, the phy transmits a remote confirmation packet with the ok bi t set, subsequently signals tx_suspend to the connected peer phy with the port which specified by the port field in t he remote command packet, and then the phy port transitions to the suspended state. the other is when the receipt of a rx_suspend or rx_disable_notify signal. when the port observes rx_suspend, it transmits tx_suspend to the active ports. the tx_suspend transmitted propagates unt il it reaches a leaf node. the ph y port transitions to the suspended state. the propagation of the suspended domain may be blocked by a phy compliant with ieee1394a-2000, a disabled or a suspended port. any one of a number of reasons may cause a sus pended port to attempt to re sume normal operations: ? bias is detected and ther e is no fault condition; ? a resume packet is received or transmitted by the phy; ? a remote command packet that sets the resume port command is received; or ? either port of a node without active ports detects bias. 3.3.2 suspend/resume off mode (sus/res = ?l?) ? remote command packet is ignored. ? resume packet is ignored. ? disabled, int_enable and resume_int bi ts in phy register are ignored. ? responses to remote access packet. ? detects the connection of the port in tpbias. ? output the 1.85 v voltage of the port in tpbias.
data sheet s16725ej2v0ds 21 pd72852a 3.4 pll and crystal oscillation circuit 3.4.1 crystal oscillation circuit to supply the clock of 24.576 mhz 100 ppm, use an exte rnal capacitor of 10 pf and a crystal of 50 ppm. 3.4.2 pll the crystal oscillator multiplies t he 24.576 mhz frequency by 16 (393.216 mhz). 3.5 cmc cmc shows the bus manager function whic h corresponds to the c bit of the se lf_id packet and the contender bit in the phy register when the input is high. the value of cmc can be changed with software through the link layer; this pin sets the initial value during power- on reset. use a pull-up or pull-down resistor of 10 k ? , based on the device? s specification. 3.6 pc0-pc2 the pc0-pc2 pin corresponds to the power field of the se lf_id packet and pwr_class in the phy register. refer to section 4.3.4.1 of t he ieee1394a-2000 specification for in formation regarding the pwr_class. the value of pwr can be changed with software through the link layer controller; this pin sets the initial value during power-on reset. use a pull-up or pull-down resistor of 10 k ? based on the application. 3.7 resetb connect an external capacitor of 0.1 f between the resetb pin and gnd. if t he voltage drops below 0 v, a reset pulse is generated. all of the circ uits are initialized, including t he contents of the phy register. 3.8 ri1 connect an external resistor of 9.1 k ? between the ri1 pin and gnd to limit the lsi?s current.
data sheet s16725ej2v0ds 22 pd72852a 4. phy/link interface 4.1 initialization of link power status (lps) and phy/link interface the lps pin monitors the on/off status of the link power state. this pin is used during the phy/link interface enable/disable (initialization). reset when the lps input pin is low for tlps_reset: ? ctl0, ctl1 and d0-d7 output low (when the isolation barrier is hi-z). ? sclk continuously supplies the clock signal to the link. disable when the lps input pin is low for tlps_disable: ? ctl0, ctl1, d0-d7 continue to output low as tlps_reset has already occurred (when the isolation barrier is hi-z). ? sclk to link stops and it outputs low (when the isolation barrier is hi-z). table 4-1. lps timing parameters parameter symbol min. max. unit lps = low propagation delay (with isolation barrier) t lpsl 0.09 1.00 s lps = high propagation delay (with isolation barrier) t lpsh 0.09 1.00 s reset active t lps_reset 1.2 2.75 s disable active t lps_disable 25 30 s setup time when using isolation barrier t restore 15 20 s figure 4-1. lps waveform when connected to isolation barrier t lpsh t lpsl
data sheet s16725ej2v0ds 23 pd72852a figure 4-2. phy/link interface reset and disable t lps_reset t restore t lps_disable t restore d, ctl, lreq lps lps (with isolation barrier) sclk d, ctl, lreq lps lps (with isolation barrier) sclk (a) reset (b) disable 4.2 link-on indication when the power supply of link is off (lps is low and the inte rnal phy register link_active bit is 0), the pin lkon outputs a clock of 6.144 mhz according to the following conditions: ? link-on packet is received. ? when any bit of the pd72852a phy register?s loop, pwr_fail, timeout or port_event becomes 1, and either lps or the link_active bit is 0. table 4-2. link-on timing parameter min. max. unit frequency 4 8 mhz duty cycle 40 60 % propagation delay before the link becomes active (lps is asserted and the link_active bit in the phy register is 1). 500 ns ? if lps or the link_active bit is 0, the link is considered inactive. when the link is inactive and any of loop, pwr_fail, ti meout, port_event becomes 1, then link-on is asserted high. ? when the link is active (both lps and link_active become 1) and loop, pwr_fa il, timeout and port_event become 1, status transfer is s ent on the phy/link interface. ? the pd72852a activates the phy/link interface when lps is 1, regardless of the value of the link active bit.
data sheet s16725ej2v0ds 24 pd72852a 4.3 phy/link interface operat ion (ctl0, ctl1, lreq, d0-d7) the phy/link interface consis ts of the following operations: ? status transfer to the link layer controller by ctl ? transmit packet ? receive packet ? request from the link layer controller by lreq 4.3.1 ctl0, ctl1 ctl0, ctl1 controls the phy/link inte rface as shown in the table 4-3. table 4-3. ctl controls phy ctl0,ctl1 type content 00 idle phy is in idle function 01 status phy transmitting status information to link 10 receive phy receiving data from the link 11 grant phy allows link to transmit data this is the operation by which, after grant, the li nk obtains the right to control the interface. table 4-4. ctl controls link ctl0,ctl1 type content 00 idle link completes the packet transmissi on and releases the phy/link interface. 01 hold 1) link transmits hold until the data is ready for transmission. 2) link transmits the interface connect packet. 10 transmit link transmits the data to phy. 11 - not used. 4.3.2 lreq access to the phy register and the bus is controlled from the link layer c ontroller through the lreq pin of phy. figure 4-3. lreq and ctl timing lr0 lr1 lr2 lr3 lr (n-2) lr (n-1) c a c b lreq ctl0,ctl1 c a : ctl before generation of lreq c b : ctl during lreq execution
data sheet s16725ej2v0ds 25 pd72852a (1) lreq format ? bus request table 4-5. bus request format bit type content 0 start signal that starts a request : 1 1-3 request bus request type: 000: immreq acknowledge packet transmit 001: isoreq isochronous packet transmit 010: prireq cycle start packet transmit 011: fairreq asynchronous packet transmit 4-6 speed transmit speed: 000: 100 mbps 010: 200 mbps 100: 400 mbps other: reserved 7 stop end request signal : 0 (optional) ? phy register read request table 4-6. read request register format bit type content 0 start signal that starts a request : 1 1-3 request read request. 100 : readreq 4-7 access address phy register address. 8 stop end request signal : 0 ? phy register write request table 4-7. write request register format bit type content 0 start signal that starts a request : 1 1-3 request write request. 101 : writereq 4-7 access address phy register address. 8-15 write data write data. 16 stop end request signal : 0
data sheet s16725ej2v0ds 26 pd72852a ? acceleration controller table 4-8. acceleration controller request format bit type content 0 start signal that starts a request : 1 1-3 request 110 : acc ctrl accelerate controller 4 access address 0: accelerate disable 1: accelerate enable 5 stop end request signal : 0 table 4-9. request type list bit type content 000 immreq used to acknowledge packet transmit. when idle is detected, phy immediately controls the bus. 001 isoreq used to transmit isochronous packet. phy does arbitration after isochronous gap is detected and acquires the bus. 010 prireq used for cycle master request. 011 fairreq fair request. 100 rdreg phy register read request. 101 wrreg phy register write request. 110 accctrl disable/enable of arbitration acceleration. 111 - unused. for the link to execute priority request and fair, star t the request using lreq when ctl0, ctl1 becomes idle, after one clock. when request is acknowledged, the pd72852a outputs grant to ctl0, ctl1. the link of cycle master uses prireq to transmit the cycle start packet. isoreq transmits the isochronous packet. isoreq becomes effective only as follows: ? the transmission of the cycle start packet is perfo rmed on the same isochronous period as receive. (the period until the subacti on gap is detected.) ? during isochronous packet transmit or receive. the pd72852a cancels isoreq with the subaction gap detecti on or bus reset. to meet the timing, do not issue the isoreq to phy w hen crc operation is performed. the link cancel method is described later. after the packet is received, link issues immreq as the acknowledge packet transmission. the purpose is to prevent another node from detecting subaction gap as ack_response_time. the pd72852a acquires the bus after packet receive and returns grant to ctl0, ct l1. when crc fails, before link detects grant, assert 3 idle cycles to ctl0, ctl1. when the bus reset is generated, the unprocessed requests are canceled. the pd72852a updates the data of the write request regist er and the contents of the read register are changed. the contents of t he register of the spec ified address are output to the link as a status transfer in the read request register, when the status transmission is interrupted by transmi tting/receiving packets, the status transmission will re-start from the first bit afte r completing the transmit/receive of the packets. the bus request (immreq, isoreq, prir eg, fairreq) is completed (in ca se of immreq, isoreq, when the subaction gap is detected) when the packet is trans mitted or canceled by canceling the bus request.
data sheet s16725ej2v0ds 27 pd72852a (2) lreq rules the link request and the stat us of the serial bus are asynchronous ; the bus request can be canceled by the status of the serial bus. the following rules apply to a request by lreq: ? link cannot issue a bus request (immr eq, isoreq, prireq, fairreq) if gr ant is given to an lreq request or until the link?s request is canceled. the request can be canceled by the pd72852a if it detects subaction gap at immreq, isoreq. ? do not issue a rdreg or wrreg request when the st atus transmission is not co mpleted by the read request register. ? all of the bus requests (immreq, isoreq, pr ireq, fairreq) are canceled by a bus reset. in addition, there is a limitation in t he request of lreq according to the st ate of ctl as shown in table 4-10. table 4-10. rules for other requests request state of ctl in c a to which lreq is allowed when phy drives ctl lreq issues permission when link drives ctl note fair, priority idle, status wrong fair, priority request cannot be issued until the unprocessed bus request is completed. immediate receive, idle wrong link issues the request after completing the decoding of destination_id, when the acknowledge packet is ready. after the packet is received, it is necessary to transmit the first bit of the request within four cycles. isochronous any correct if the isochronous packet transmission is prepared for the isochronous period, it is issued. do not issue the request to transmit the isochronous packet appending to the currently transmitted isochronous packet (using hold). register read register write any correct do not issue this request if the unprocessed read request has not been completed. accctrl any correct to set acceleration bit 0: when the isochronous period starts, if the enab_accel bit is one, cycle slave should adjust accelerate bit to 0. to set acceleration bit 1: do not set the cycle master. it is issued when the isochronous period ends.
data sheet s16725ej2v0ds 28 pd72852a table 4-11. phy operation before lreq request to the ctl function changes request state of ctl in c b after lreq was issued operation of the phy fair, priority receive ? hold the request if the acceleration of arbitration packet transmitted with enable is 8 bits (ack). except for 8 bits, the requests are ignored. ? ignore the request when the acceleration of arbitration is disabled. grant arbitration won. idle, status excluding when the bus reset is generated, hold the requests. immediate grant receive the packet is being transmitted to link. request hold. idle, status excluding when the bus reset is generated, hold the request. isochronous transmit idle (dri ven by link) request hold. grant arbitration won. receive request hold. status request is ignored w hen sub-action gap is detected. idle register read any (driven by link) grant request hold. receive request hold. status hold the request until the corresponding register value is returned. idle register write, acceleration control any request is completed. 4.3.3 sclk timing table 4-12. sclk timing timing constant comment min. max. unit bus_to_link_delay period from receiving rx_data_prefix until receive to ctl is output. 2 9 sclk cycle data_prefix_to_grant period when the grant is output to ctl after tx_data_prefix is output to a port. 25 sclk cycle link_to_bus_delay period when tx_data_end is output to all ports after transmitting the packet by link after idle was asserted to ctl. 2 5 sclk cycle max_hold maximum period when hold can be asserted by link to confirm grant. 47 sclk cycle
data sheet s16725ej2v0ds 29 pd72852a 4.4 acceleration control enable of ack-acceleration and fly-by on the same is ochronous period may create a problem. the isochronous cycle may extend unintentionally when transmitting the asynchronous packet by a node using ack-acceleration and fly- by. to avoid this problem, link should control disable/enable of these enhancements (ack-acceleration, fly-by), by acceleration control requests. cycle master cannot issue the acceleration control request. the enhancements should not be used from the generation of the local cycl e synchronization event to the confirmation of cycle start. in this per iod, all links except for cycle master use acceleration control as follows: ? do not issue fair nor priority request to link after generating local cycle synchroni zation, if the acceleration control request?s accelerate bit is not set to 0. ? link must not use hold when trans mitting continuous primary asynchronous packet after the acknowledge packet, except after ack_pending to comp lete the split transaction. ? ending the link during the is ochronous period issues the acceleration contro l request to set the accelerate bit to 1, enabling these enhancements. the pd72852a does not require setting the acceleration control during isochronous transmit to enable the isochronous request fly-by acceleration. it is not necessary to issue acceleration control request w hen the cycle master is absent from the serial bus. these enhancements are enabled if the enab_accel bit in the phy register is set. the pd72852a supports variable acceleration controlled by the acceleration control during power-on reset.
data sheet s16725ej2v0ds 30 pd72852a 4.5 transmit status pin d0, d1 of the pd72852a transmits status information to the link . status is asserted to ctl while transmitting status. the status transmission is interr upted if the serial bus receives a pa cket which contains states other than status to ctl. between two status transmissions, a ssert idle to ctl for at least one sclk cycle. the pd72852a transmits status in 16 bits as follows: ? in response to the register request ? after deciding the new physical_id for the self_id period resetting the bus (after a self_id packet is transmitted) the event indication is the only 4-bit transmission of the pd72852a. figure 4-4. status timing 00 01 01 00 00 00 s0,s1 s2,s3 00 00 phy ctl0,ctl1 phy d0-d7 01 s14, s15 table 4-13. status data format bit(s) name description 0 arb_reset_gap arbitration reset gap detect 1 subaction_gap subaction gap detect 2 bus_reset_start bus reset detect 3 phy_interrupt either of the following states is detected: ? the topology of the bus is a loop ? voltage drop on the power cable ? arbitration state machine timeout ? port event 4-7 address phy register address 8-15 data register data the bits already transmitted are set to 0. example if the status transmission is interrupted after s0, s1 bi t was transmitted, then in the next status transfer, s0, s1 becomes 0. therefore one of the following si tuations will occur when the pd72852a re-transmits status after an interruption of the status transmission: ? at least one bit of s0-s3 is 1 ? the phy register data contains the interrupt status information the status transmission always begins with s0, s1. if the link executes read request, and s ubaction gap and arbitration reset gap are det ected, priority is given to the transmission of gap status, postponing the response to the register read request.
data sheet s16725ej2v0ds 31 pd72852a 4.6 transmit the pd72852a arbitrates the serial bus using link?s lreq. ? when the pd72852a acquires the bus, a grant per iod of 1 sclk is executed to ctl0, ctl1. after that, an idle period of 1 sclk cycle is executed. ? link controls the interface execut ing idle, hold of transmit to ctl0, ctl1 after 1 sclk cycle when grant from phy is detected. ? before asserting hold and transmi t, assert 1 idle cycle. do not ex ecute idle for 2 or more cycles. ? if the packet transmit is not ready, the hold period can be extended up to max_hold. ? the pd72852a outputs data_prefix to the serial bus while hold is being asserted to ctl. ? when the packet transmit is ready, link outputs the first bit of the packet and transmit is asserted to ctl at the same time. ? after transmitting the last bit of the packet, link outputs for id le or hold to ctl for 1 cycle. after that, it outputs idle for 1 cycle. when phy/link releases the bus, output low to ctl and d0-d7 within 1 cycle. figure 4-5. transmit timing 00 11 00 zz zz zz zz zz zz zz zz zz 00 00 00 00 zz zz zz zz zz zz zz zz zz 00 zz zz zz 00 01 01 10 10 10 10 00 00 zz zz zz zz 00 00 00 d0 d1 d2 d n 00 00 zz zz zz zz zz 00 00 11 00 zz zz zz zz zz zz zz 00 00 00 00 zz zz zz 10 10 01 00 zz zz zz zz 01 10 10 d n-1 d n sp 00 zz zz zz zz 00 d0 d1 zz zz 01 00 (a) single packet phy ctl0,ctl1 phy d0-d7 link ctl0,ctl1 link d0-d7 (b) concatenated packet phy ctl0,ctl1 phy d0-d7 link ctl0,ctl1 link d0-d7 zz zz 00 00 note in case of packet transmission after grant, before actual transmission, hold does not need to be asserted. link can transmit continuous packe ts without releasing the bus. ? hold is asserted to ctl. this function is used when the link transmits continuous packets after acknowledge and isochronous packets. link outputs the transfer rate signal of the following packet to d0-d7 and asserts hold simultaneously. ? after hold is detected by min_packet_separation, the pd72852a outputs grant to ctl.
data sheet s16725ej2v0ds 32 pd72852a ? link controls the interface by gener ating idle, hold or transmit to ctl0, ctl1, after 1 sclk cycle when grant from phy is detected. ? assert 1 idle cycle before asserting hold and transmit (do not output 2 or more id le cycles). when the packet transmission is not ready, assert hold. the hold output period after grant is det ected should not exceed the period provided by max_hold. the following limitations exist though link can transmit the concatenated packet wi th a different transfer rate. link cannot transmit other than s100 connecti ng packets after s100 (concatenated) packets have been transmitted. a new request to transmit must be issued in order to transmi t s100 packets at a transfer rate of s200 or more. if the enab_multi bit in the phy register is 0, the pd72852a assumes the same speed as the first packet, for all of the concatenated packets. at the end of packet transmission, link assert s idle to ctl for a period of 2 cycles. after sampling idle from link, the pd72852a asserts idle to ctl for a period of 1 cycle. 4.7 cancel this section describes how link operates, when after t he bus has been acquired by the request of lreq, there is no data transmission. in this case, a null packet with no data is transmitted to the serial bus (data_prefix data_end). following are two method for canceling the link: 1. as explained in section 4. 6, the link outputs idle or hold, then outputs transmit to ctl after confirming grant. here, the link asserts idle for two cycles to ctl, then switches to high impedance. the pd72852a confirms cancel at the sec ond idle cycle. to prevent the bus from switching to high impedance, a third idle cycle is needed. figure 4-6. link cancel timing (after grant) 00 11 00 zz zz 00 00 00 00 zz zz 00 zz zz zz 00 00 zz zz zz zz 00 00 zz phy ctl0,ctl1 phy d0-d7 link ctl0,ctl1 link d0-d7 zz zz 00 00 2. to cancel after asserting hold, assert idle between two cycles; it sw itches to high impedance. this method cancels the packet transmission connection (conc atenated) after grant is received. the pd72852a cancels with the next idle cycle of hold. to prevent ctl from switching to high impedance, assert a second idle cycle.
data sheet s16725ej2v0ds 33 pd72852a figure 4-7. link cancel timing (after hold) 00 11 00 zz zz zz zz zz 00 00 00 00 zz zz zz zz zz 00 zz zz zz 00 01 01 00 00 zz zz zz zz 00 00 00 00 00 zz phy ctl0,ctl1 phy d0-d7 link ctl0,ctl1 link d0-d7 4.8 receive this section shows the operat ion when the packet is received from the serial bus. ? when the pd72852a detects data_prefix on the serial bus, it asserts receive to ctl and all of the d pins assume the logic value of 1. ? the pd72852a shows the speed code of the transfer rate ahead of the packet using bits d0-d7. transmitting the speed code with the speed signal is t he protocol of the phy/link interf ace. the speed code is not included in the crc calculation. ? the pd72852a continues to assert receive to ct l until the packet is finally transmitted. ? idle is asserted to ctl, indicati ng completion of the packet transmission. figure 4-8. receive timing 00 10 10 10 10 10 00 00 ff ff d0 d1 d n 00 phy ctl0,ctl1 (binary) phy d0-d7 (hex) 10 sp 00 00 the packet transfer rate of the serial bus depends on the topology of the bus. the pd72852a checks if the node can receive at the faster transfer rate. at this time, data_prefix data_end is transmitted to the pd72852a. after data_prefix is transmitted to the link, receive from the serial bus is co mpleted, asserting idle. table 4-14 shows the speed code encoding. table 4-14. speed encoding d0-d7 data rate transmitted observed 00000000 00xxxxxx s100 01000000 0100xxxx s200 01010000 01010000 s400 11111111 11xxxxxx data prefix
data sheet s16725ej2v0ds 34 pd72852a 5. cable phy packet the node on the serial bus transmits and rece ives the phy packet to control the bus. the phy packet is composed of 2 quadlets (64-bit); the sec ond quadlet (32-bit) contains the inverse value of the first quadlet. the phy packet is transmitted at a transfer rate of s100. all of the phy packets receiv ed from the serial bus are transmitted to the link. though the phy packet from the pd72852a is transmitted to the link, the phy packet which was transmitted from the link of the node is not transmitted to the link. there are four types of phy packets, as follows: ? self_id packet ? link-on packet ? phy configuration packet ? extended phy packet the self_id packet transmitt ed automatically by the pd72852a is also transmitted to the link of a local node. the pd72852a phy packet receive from the serial bus operat es similar to the phy packet transmitted by the link (when the packet transmission to the link is executed). 5.1 self_id packet during the self_id phase of the initialization or when the ping packet responds, the pd72852a transmits the self_id packet. figure 5-1. self_id packet format 10 phy_id 0 l gap_cnt sp rsv c pwr p0 p1 p2 i m logical inverse of the first quadlet table 5-1. self_id packet field description phy_id physical id of the node. l logical product of link_active and lps in the phy register. gap_cnt gap_count value in the phy register. sp physpeed 10 (corresponds to 98.304, 196.608, 393.216 mbps). c c bit values in the phy register. pwr pwr value in the phy register. 000: the node does not need the power supply. no power repeat. 001: obtains power supply for the node. can supply 15 w or more. 010: obtains power supply for the node. can supply 30 w or more. 011: obtains power supply for the node. can supply 45 w or more. 100: the node consumes 3 w maximum power. 110: the node consumes 3 w maximum power. at least 3 w are necessary to enable link. 111: the node consumes 3 w maximum power. at least 7 w are necessary to enable link. i it shows that the node issued bus reset and the bus was reset. m read as 0. rsv read as 00.
data sheet s16725ej2v0ds 35 pd72852a 5.2 link-on packet the pd72852a outputs the link-on signal of 6.144 mhz from the pin lkon when receiving the link-on packet. figure 5-2. link-on packet format 01 phy_id 0000 0000 0000 0000 0000 0000 logical inverse of the first quadlet table 5-2. link-on packet field description phy_id physical_id of the destination of the link-on packet 5.3 phy configuration packet use the phy configuration packet to set the gap count for the bus. figure 5-3. phy configuration packet format 00 root_id r t gap_cnt 0000 0000 0000 0000 logical inverse of the first quadlet table 5-3. phy configuration packet field description root_id sets the physical_id node as root contender (for the next reset). r when this bit is set to 1 and the phyisical_id of the node corresponds to the rootid of this packet, the pd72852a sets the force_root bit. the force_root bit is cleared if there is discrepancy. t if this bit is 1, the gap_cnt value of this packet is used as the gap_count value. the gap_count value must not be cleared by the following bus reset, set the gap_count_reset_disable flag in the pd72852a to true. gap_cnt when this packet is received, the gap count is set to this value. while it remains effective for the next bus reset, it will be cleared by the second bus reset to 3fh. remark applying 0 to both r,t, regards the following packets as extended phy packets, the phy configuration is not recognized. 5.4 extended phy packet an extended phy packet is defined when bot h the r (in the phy configuration pa cket) and t bits are transmitted as 0. the extended phy packet does not influence t he force_root_bit and the gap_count bit on any node. following are the types of extended phy packets: ? ping packet ? remote access packet ? remote reply packet ? remote command packet ? remote confirmation packet ? resume packet
data sheet s16725ej2v0ds 36 pd72852a 5.4.1 ping packet when the pd72852a receives the ping packet, it will transmit the self_id packet within the response_time. figure 5-4. ping packet format 00 phy_id 00 type (0) 00 0000 0000 0000 0000 logical inverse of the first quadlet table 5-4. ping packet field description phy_id physical id of the destination node of the ping packet type indicates that there is a ping packet with a value of 0 5.4.2 remote access packet the remote access packet reads information in the phy register of another node. t he phy specified by the remote access packet transmits the value in the register using the remote reply packet. figure 5-5. remote access packet format 00 phy_id 00 type page port reg reserved logical inverse of the first quadlet table 5-5. remote access packet field description phy_id physical id of the destination node of the remote access packet type 1 = read register (base register), 5 = read register (page register) page specifies the page of the phy register port specifies the register of each port in the phy register reg specifies the address when reading the base register. in case of the page and port registers, specifies the address with 1000+reg.
data sheet s16725ej2v0ds 37 pd72852a 5.4.3 remote reply packet the pd72852a transmits the value in the r egister by using the remote reply packet as a response to the remote access packet. figure 5-6. remote reply packet format 00 phy_id 00 type page port reg data logical inverse of the first quadlet table 5-6. remote reply packet field description phy_id physical id of the node (node?s original packet transmit) type 3 = register read (base register), 7 = read register (page register) page used when specifying the page of the phy register port used to specify the register of each port in the phy register reg specifies the address when reading the base register. in case of the page and port registers, specify the address with 1000+reg. data contents of the specified register 5.4.4 remote command packet use the remote command packet to operate the f unction of the port of the phy of another node. figure 5-7. remote command packet format 00 phy_id 00 type(8) 000 port 0000 0000 cmnd logical inverse of the first quadlet table 5-7. remote command packet field description phy_id physical id of the destination packet type extended phy packet type; set to 8 for remote command packet port port of the phy of the operating node cmnd command 0: nop 1: disables the port after trans mission of the tx_disable_notify 2: suspend initiator 4: clears to 0 the fault bit of the port 5: enables the port 6: resumes the port
data sheet s16725ej2v0ds 38 pd72852a 5.4.5 remote confirmation packet the pd72852a transmits the remote confirmation when t he remote command packet is received, responding whether cmnd can be executed. figure 5-8. remote confirmation packet format 00 phy_id 00 type(a 16 ) 000 port 000 f c b d ok cmnd logical inverse of the first quadlet table 5-8. remote confirmation packet field description phy_id physical id of the node (node?s original packet transmit) type extended phy packet type; set to a 16 for remote confirmation packet port port set from the remote command packet f fault bit value of the phy register of this port c connected bit value of the phy register of this port b bias bit value of the phy register of this port d disable bit value of the phy register of this port ok 1 indicates executing; otherwise it is 0 cmnd specifies the command value with the remote command packet 5.4.6 resume packet when the pd72852a receives the resume packet, all of the ports that were suspended resume the connection. the resume packet does the broadcast. figure 5-9. resume packet format 00 phy_id 00 type (f 16 ) 00 0000 0000 0000 0000 logical inverse of the first quadlet table 5-9. resume packet field description phy_id physical id of the original packet transmit type extended phy packet type; set to f 16 for resume packet
data sheet s16725ej2v0ds 39 pd72852a 6. electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v ddm ?0.5 to +4.6 v input voltage v in ?0.5 to v dd +0.5 v output voltage v out ?0.5 to v dd +0.5 v storage temperature t stg ?40 to +125 c caution product quality may suffer if the absolute maximu m rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. a cmos device may cause unusual operation or destruction by latch-up phenomenon. for your safety, be careful of the factor (serge, noise, st atic electricity) considered as external stress to input/output pins. in order to avoid outbreak of heat/destruction of the device/board/equipment by an over-current continuing input, please prepare the curre nt restrictions below 1.5 [a] as v cc input. recommended operating ranges parameter symbol condition min. typ. max. unit source power node 3.0 3.3 3.6 v power supply voltage v dd non-source power node 2.7 note 3.0 3.6 v operating temperature t a 0.0 70.0 c power dissipation p d 440 mw note for a node does not source power.
data sheet s16725ej2v0ds 40 pd72852a dc characteristics common parameter symbol condition min. typ. max. unit note 1 68 ma note 2 60 ma note 3 41 ma note 4 31 ma supply current i dd note 5 115 a notes 1. transmit maximum packet (all ports transmitting maxi mum size isochronous packet - 4096 bytes, sent on every isochronous interval, s400, data value of cccccccch), v dd = 3.3 v, t a = 25c 2. repeat typical packet (receiving on one port dv pa ckets on every isochronous interval, s100, and transmitting on the other port), v dd = 3.3 v, t a = 25c 3. idle (one port receiving and one port transmitting cycle starts), v dd = 3.3 v, t a = 25c 4. 1 port receiving cycle start packet only, v dd = 3.3 v, t a = 25c 5. suspend mode, v dd = 3.3 v, t a = 25c phy/link interface parameter symbol condition min. typ. max. unit high-level output voltage v oh ctl0, ctl1, d0-d7, lkon, sclk, i oh = ?9 ma, v dd > 3 v v dd ?0.45 v ctl0, ctl1, d0-d7, lkon, sclk, i oh = ?4 ma, v dd = 2.7 v v dd ?0.4 v low-level output voltage v ol ctl0, ctl1, d0-d7, lkon, sclk, i oh = +9 ma, v dd > 3 v 0.4 v ctl0, ctl1, d0-d7, lkon, sclk, i oh = +4 ma, v dd = 2.7 v 0.4 v high-level input voltage v ih lps, spd, direct, pc0-pc2, sus/res, cmc 0.7v dd v low-level input voltage v il lps, spd, direct, pc0-pc2, sus/res, cmc 0.2v dd v high-level input voltage (schmitt) v ihs ctl0, ctl1, d0-d7, lreq, v dd > 3 v 0.456v dd +0.3 0.456v dd +0.9 v low-level input voltage (schmitt) v ils ctl0, ctl1, d0-d7, lreq, v dd > 3 v 0.456v dd ?0.9 0.456v dd ?0.3 v high-level input current i ih ctl0, ctl1, d0-d7, v i = v dd , direct = 0 v ?10 a lps, spd, direct, pc0-pc2, sus/res, cmc, v i = v dd ?10 a low-level input current i il ctl0, ctl1, d0-d7, lkon, sclk, v i = 0 v, direct = 0 v 10 a lps, spd, direct, pc0-pc2, sus/res, cmc, v i = 0 v 10 a
data sheet s16725ej2v0ds 41 pd72852a cable interface parameter symbol condition min. typ. max. unit cable input, 100 mbps operation 142 260 mv cable input, 200 mbps operation 132 260 mv differential input voltage v id cable input, 400 mbps operation 118 260 mv 100 mbps speed signaling off 1.165 2.515 v 200 mbps speed signaling 0.935 2.515 v tpb common mode input voltage v icm 400 mbps speed signaling 0.523 2.515 v differential output voltage v od cable output (test load 55 ? ) 172.0 265.0 mv 100 mbps speed signaling off 1.665 2.015 v 200 mbps speed signaling 1.438 2.015 v tpa common mode output voltage v ocm 400 mbps speed signaling 1.030 2.015 v 100 mbps speed signaling off ?0.81 +0.44 ma 200 mbps speed signaling ?4.84 ?2.53 ma tpa common mode output current i cm 400 mbps speed signaling ?12.40 ?8.10 ma power status threshold voltage v th cps 7.5 v tpbias output voltage v tpbias 1.665 2.015 v
data sheet s16725ej2v0ds 42 pd72852a ac characteristics phy/link interface parameter symbol condition min. typ. max. unit d, ctl, lreq setup time t su 5 ns d, ctl, lreq hold time t hd 0 ns d, ctl output timing t d 0.5 9 ns sclk cycle time t sclk 20 ns sclk high level time t sclkh 9 11 ns sclk low level time t sclkl 9 11 ns lkon cycle time t linkon 160 ns link interface timing (sclk, lkon) sclk t sclkl lkon t linkon t sclkh t sclk
data sheet s16725ej2v0ds 43 pd72852a link interface timing (ctl, d) sclk ctl0,ctl1 d0-d7 transmit receive ctl0,ctl1 d0-d7 t d t d t d t d t d t d t su t h t su t h link interface timing (lreq) sclk lreq t su t h cable interface parameter symbol condition speed min. typ. max. unit tpa, tpb transfer jitter t jitter between tpa and tpb 0.15 ns tpa strobe, tpb data transfer t skew between tpa and tpb 0.10 ns s100 0.5 3.2 ns s200 0.5 2.2 ns tpa, tpb rise time/fall time t r /t f 10 % to 90 %, via 55 ? and 10 pf s400 0.5 1.2 ns
data sheet s16725ej2v0ds 44 pd72852a 7. application circuit example ? ieee1394 interface agnd direct ic(al) agnd agnd av dd resetb dv dd dgnd lkon lps dv dd spd fnsel lreq dgnd dgnd sclk ic(dl) dv dd ctl0 ctl1 dgnd d0 d1 dv dd d2 d3 dgnd d4 d5 dgnd 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cps av dd cmc ic(al) pc2 pc1 pc0 av dd agnd xi xo dgnd dv dd sus/res d7 d6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 tpbias1 av dd tpa1p tpa1n tpb1p tpb1n agnd tpbias0 av dd tpa0p tpa0n tpb0p tpb0n agnd ri1 agnd gnd gnd av ddpower (3.3 v) 22 f note common mode choke. recommendation : tdk part no. acm2012-121 : murata part no.plp31dn161sl4 10 pf 0.1 f 9.1 k ? (0.5%) power class programming 10 pf 24.576 mhz 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 56 ? 56 ? 56 ? 56 ? 56 ? 56 ? 56 ? 56 ? 5.1 k ? 270 pf 5.1 k ? 270 pf note note 0.1 f 1 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f 22 f 100 k ? 390 k ? dv ddpower (3.3 v) 0.1 f v p (cable supply voltage)
data sheet s16725ej2v0ds 45 pd72852a 8. package drawing m 48 32 33 64 1 17 16 49 s n s j detail of lead end r k m i s l t p q g f h 64-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 1.25 12.0 0.2 h 0.22 0.05 c 10.0 0.2 f 1.25 i j k 0.08 0.5 (t.p.) 1.0 0.2 l 0.5 p 1.4 q 0.1 0.05 t 0.25 s 1.5 0.10 u 0.6 0.15 s64gb-50-8eu-2 r3 + 4 ? 3 n 0.08 m 0.17 + 0.03 ? 0.07 a b cd u note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition.
data sheet s16725ej2v0ds 46 pd72852a 9. recommended soldering conditions the pd72852a should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, c ontact your nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http:// www.necel.com/pkg/en/m ount/index.html) table 9-1. surface mounting type soldering conditions pd72852agb-8eu: 64-pin plastic lqfp (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 sec. max. (at 210c or higher). count: three times or less exposure limit: 3 days note (after that prebake at 125c for 10 hours) ir35-103-3 partial heating pin temperature: 300c max., time: 3 sec. max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65 % rh or less for the allowable storage period.
data sheet s16725ej2v0ds 47 pd72852a 1 2 3 4 5 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. pay attention to charging with static electricity of the device or the surface of the device package in case the handing of this product and the production manufacturing process, please use the ionizer for this device to eliminate static electricity. notes for cmos devices
pd72852a firewire is a trademark of apple computer, inc. i.link is a trademark of sony corporation. intel is a trademark of intel corporation. the information in this document is current as of march, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ?

▲Up To Search▲

Price & Availability of UPD72852AGB-8EU

	To Download UPD72852AGB-8EU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .